1. Field of the Invention
The present invention relates to display devices and, more particularly, to plasma discharge display devices. Still more particularly, the present invention relates to a plasma discharge panel having a reduced number of external drive lines and associated drive circuits.
2. Prior Art
U.S. Pat. No. 3,559,190 issued to D. L. Bitzer et al on Jan. 26, 1971, and U.S. Pat. No. 3,499,167 issued to T. C. Baker et al on Mar. 3, 1970, typify the display device commonly known as the plasma panel. Such panels typically include a plurality of individual gas discharge sites or cells defined by the intersection of horizontal and vertical conducting lines placed on either side of a sandwich arrangement including parallel dielectric layers enclosing an ionizable gas. The effect, then, is to define by the intersection of the conductors a rectangular matrix of gas discharge cells. For the case where there are R rows and C columns there are therefore a total number of R .times. C individual gas discharge cells.
A considerable portion of the expense in manufacturing plasma panels has been found to be the drive circuitry for applying pulse or sinusoidal signals to the individual row and column conductors associated with a plasma panel. The drive circuits include means for establishing, maintaining and terminating plasma glow discharges at each of the cells. In general, a separate driver is provided in the prior art for each row and each column in the array. A number of attempts have been made to simplify the drive circuitry associated with plasma panels. See, for example, W. E. Johnson et al, "A Quarter-Million-Element AC Plasma Display with Memory" and G. W. Dick, "Low Cost Drivers for Capacitively Coupled Gas Plasma Display Panels," both appearing in Proceedings of the SID, Vol. 13, No. 1, First Quarter 1972; and U.S. Pat. No. 3,689,912 issued to G. W. Dick on Sept. 5, 1972.
Another technique common in addressing memory arrays, e.g., may also be used to some advantage in addressing plasma panels. In particular, matrix crosspoint selection structures useful in some applications are described in U.S. Pat. No. 3,665,400 issued May 23, 1972 to D. D. Leuck.
Still another plasma panel addressing scheme involves the application of additive and subtractive pulses to selected and non-selected plasma cells. Such techniques are described, e.g., in T. N. Criscimagna, "Additive Pulses `Turn On` Display Cells -- Reliably," Electro-Optical Systems Design, Aug. 1971, pp. 32-37.
One effort to simplify the addressing requirements for a plasma panel by partial decoding at the plasma display sites, i.e., per cell partial decoding, is described in J. D. Schermerhorn, "Internal Random Access Address Decoding in AC Plasma Display Panel," Digest of Technical Papers 1974 SID International Symposium, May 1974, pp. 22-23. The per cell partial decoding described in this latter paper, however, is based on a selective erase process; no direct writing (initiating of a glow discharge) at individual cells is possible using the Schermerhorn technique. Another useful reference directed to plasma panel access circuitry simplification is U.S. Pat. No. 3,824,580 issued July 16, 1974 to C. R. Bringol.
It is, therefore, an object of the present invention to provide a plasma panel having a decreased number of external drive lines and, consequently, a reduced number of associated drive circuits.
It is a further object of the present invention to provide for individual direct addressing (writing or erasing) at each individual display site.